1. Field of the Invention
The present invention relates in general to pipelined processors and, in particular, to a pipelined processor for generating a single cycle pipeline stall. Still more particularly, the present invention relates to a pipelined processor processing instructions in order to generate a single cycle pipeline stall in response to a detection of a dependency.
2. Description of the Related Art
A pipelined data processing system is a data processing system which includes a microprocessor architecture which is capable of executing multiple instructions per clock cycle. In order to execute multiple instructions per cycle, multiple independent functional units that can execute concurrently are required. In an in-order pipelined processor, these multiple instructions are executed in their original sequence.
Some of the instructions are single cycle instructions which complete their processing in a single clock cycle. Others instructions require more than one clock cycle to complete processing.
Dependencies often occur during instruction processing. One type of dependency occurs when one register writes a value to a register which must be read by another, later instruction. When the instruction writing a value to a register takes more than one cycle to execute, the later instruction which reads that value stored in the register must be stalled until the first instruction completes its execution. Therefore, pipeline stalls must be inserted into the instruction stream in order to properly execute the instructions.
In known systems, a determination regarding whether to insert a pipeline stall due to a dependency must be made in a single cycle, if a single-cycle stall is to be generated.
Mechanisms that use multiple cycles to determine if an instruction can be dispatched or must be stalled cause multiple-cycle stalls. Taking multiple cycles to determine stall conditions is advantageous for improving processor frequency, but multiple stall cycles are disadvantageous for processor performance as measured in cycles per instruction (CPI).
Therefore a need exists for a pipelined processor processing instructions in order for generating a single cycle pipeline stall in response to a detection of a dependency, where the detection mechanism takes multiple cycles to control instruction dispatch.
A pipelined processor and method are disclosed for speculatively determining dependencies. The processor processes a plurality of instructions in order. A speculative detection circuit which takes multiple clock cycles to operate determines whether a dependency exists. The speculative detection circuit inserts a single-cycle pipeline stall only in response to a determination that a speculative dependency exists.
The above as well as additional objectives, features, and advantages of the present invention will become apparent in the following detailed written description.